Datasheet Summary
74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
SCAS014C
- AUGUST 1987
- REVISED APRIL 1996
D, N, OR PW PACKAGE (TOP VIEW)
1A 1Y 2Y GND GND 3Y 4Y 4B
1 2 3 4 5 6 7 8
16 1B 15 2A 14 2B 13 VCC 12 VCC 11 3A 10 3B
9 4A description
This device contains four independent 2-input AND gates. It performs the Boolean function
+ + )Y A
- B or...