Texas Instruments 74ACT11002
The 74ACT11002 is characterized for operation from – 40°C to 85°C.| Part No. | 74ACT11002 |
|---|---|
| Datasheet | 74ACT11002 Download |
| Manufacturer |  Texas Instruments |
| Description | QUADRUPLE 2-INPUT POSITIVE-NOR GATES |
| Buy | Stock & Price |
54ACT11002, 74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
● Inputs Are TTL-Voltage Compatible
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
● EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain four independent 2-input NOR gates. They perform the Boolean functions Y = ASB or Y = A + B in positive logic. The 54ACT11002 is characterized for operation over the full military temperature range of – 55°C to 125°C. logic symbol† 1 1A ≥1 16 1B 15 2A 14 2B 11 3A 10 3B 9 4A 8 4B 2 1Y 3 2Y 6 3Y 7 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. FUNCTION TABLE (each gate) INPUTS A B H X X H L L OUTPUT Y L L H SCAS003A – D2957, JUNE 1987 – REVISED APRIL 1993 54ACT11002 . . .
● Inputs Are TTL-Voltage Compatible
● Flow-Through Architecture to Optimize PCB Layout
● Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
● EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process
● 500-mA Typical Latch-Up Immunity at 125°C
● Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description These devices contain four independent 2-input NOR gates. They perform the Boolean functions Y = ASB or Y = A + B in positive logic. The 54ACT11002 is characterized for operation over the full military temperature range of – 55°C to 125°C. logic symbol† 1 1A ≥1 16 1B 15 2A 14 2B 11 3A 10 3B 9 4A 8 4B 2 1Y 3 2Y 6 3Y 7 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. FUNCTION TABLE (each gate) INPUTS A B H X X H L L OUTPUT Y L L H SCAS003A – D2957, JUNE 1987 – REVISED APRIL 1993 54ACT11002 . . .
