Datasheet Details
| Part number | ADC3568 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 4.12 MB |
| Description | 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter |
| Download | ADC3568 Download (PDF) |
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| Part number | ADC3568 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 4.12 MB |
| Description | 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter |
| Download | ADC3568 Download (PDF) |
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• 16-bit, single channel 250 and 500MSPS ADC • Noise spectral density: −160.4dBFS/Hz • Thermal Noise: 76.4dBFS • Single core (non-interleaved) ADC architecture • Power consumption: – 435mW (500MSPS) – 369mW (250MSPS) • Aperture jitter: 75fs • Buffered analog inputs – Programmable 100Ω and 200Ω termination • Input fullscale: 2VPP • Full power input bandwidth (−3dB): 1.4GHz • Spectral performance (fIN = 70MHz, −1dBFS): – SNR: 75.6dBFS – SFDR HD2,3: 80dBc – SFDR worst spur: 94dBFS • INL: ±2 LSB (typical) • DNL: ±0.5 LSB (typical) • Digital down-converters (DDCs) – Up to four independent DDCs – Complex and real decimation – Decimation: /2, /4 to /32768 decimation – 48-bit NCO phase coherent frequency hopping • Parallel/ Serial LVDS interface – 16-bit Parallel SDR, DDR LVDS for DDC bypass – Serial LVDS for decimation – 32-bit output option for high decimation 2 Applications The ADC3568 and ADC3569 (ADC356x) are 16-bit, 250MSPS and 500MSPS, single channel analog to digital converters (ADC).
The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of -160dBFS/Hz (500MSPS).
The power efficient ADC architecture consumes 435mW at 500MSPS and provides power scaling with lower sampling rates (369mW at 250MSPS).
ADC3568, ADC3569 SBASAO4A – DECEMBER 2024 – REVISED JANUARY 2025 ADC3568, ADC3569 Single-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC).
| Part Number | Description |
|---|---|
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