ADS6445 Datasheet | Texas Instruments

FEATURES - Maximum Sample Rate: 125 MSPS - 14-Bit Resolution with No Missing Codes - Simultaneous Sample and Hold - 3.5d B Coarse Gain and up to 6d B Programmable Fine Gain for SFDR/SNR Trade-Off - Serialized LVDS Outputs with Programmable Internal Termination Option - Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude down to 400 m VPP - Internal Reference with External Reference Support - No External Decoupling Required for References - 3.3-V Analog and Digital Supply - 64 QFN Package (9 mm × 9 mm) - Pin patible 12-Bit Family (ADS642X SLAS532A) - Feature patible Dual Channel Family (ADS624X - SLAS542A, ADS644X - SLAS543A) APPLICATIONS - Base-Station IF Receivers - Diversity Receivers - Medical Imaging - Test Equipment Table 1. ADS64XX Quad Channel Family ADS644X 14 Bit ADS642X 12 Bit 125 MSPS ADS6445 ADS6425 105 MSPS 80 MSPS 65 MSPS ADS6444 ADS6443 ADS6442 ADS6424 ADS6423 ADS6422 Table 2. Performance Summary SFDR, d Bc Fin = 10MHz (0 d B gain) Fin = 170MHz (3.5 d B gain) Fin = 10MHz (0 d B gain) SINAD, d BFS Fin = 170MHz (3.5 d B gain) Power, per channel, m W ADS6445 87 79 73.4 68.3 420 ADS6444 91 83 73.4 69.3 340 ADS6443 92 84 74.2 69.4 300 ADS6442 93 84 74.3 70 265 DESCRIPTION The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65 MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a pact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device includes 3.5d B coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1d B steps up to 6d B. The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (pared to a 1-wire interface) and restrict it to less than 1Gbps easing receiver design. The ADS644X also...