CD54HCT173 Overview
The CDx4HC173 and CDx4HCT173 contains four independent D-type flip-flops with shared clock (CP), reset (MR), and data enable (E1, E2) pins. Shared Control Logic One of Four D-Type Flip-Flops DQ Qx Dx R Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers....
CD54HCT173 Key Features
- Three-state buffered outputs
- Gated input and output enables
- Fanout (over temperature range)
- Standard outputs : 10 LSTTL loads
- Bus driver outputs : 15 LSTTL loads
- Wide Operating Temperature Range : -55°C to 125°C
- Balanced propagation delay and transition times
- Significant power and reduction pared to LSTTL logic ICs
- HC types
- 2 V to 6 V operation