CD54HCT174 Datasheet | Texas Instruments

Data sheet acquired from Harris Semiconductor SCHS159C August 1997 - Revised October 2003 CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset [ /Title (CD74 HC174 , CD74 HCT17 4) /Subject (High Speed CMOS Logic Hex DType Flip Flop Features - Buffered Positive Edge Triggered Clock - Asynchronous mon Reset - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH Description The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flipflops. They possess low power and speeds parable to low power Schottky TTL circuits. The devices contain six masterslave flip-flops with a mon clock and mon reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin patible to the ’LS174. Ordering Information PART...