Datasheet4U Logo Datasheet4U.com

CD74HC10M - Triple 3-Input NAND Gates

Download the CD74HC10M datasheet PDF. This datasheet also covers the CD74HC10 variant, as both devices belong to the same triple 3-input nand gates family and are provided as variant models within a single manufacturer datasheet.

General Description

This device contains three independent 3-input NAND gates.

B

C in positive logic.

Key Features

  • Buffered inputs.
  • Wide operating voltage range: 2 V to 6 V.
  • Wide operating temperature range: -55°C to +125°C.
  • Supports fanout up to 10 LSTTL loads.
  • Significant power reduction compared to LSTTL logic ICs 2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD74HC10-etcTI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CD74HC22106 QMOS 8 x 8 x 1 Crosspoint Switches with Memory Control Intersil Corporation
CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES NXP
CD74HC373E OCTAL TRANSPARENT D-TYPE LATCHES NXP
CD74HC373M OCTAL TRANSPARENT D-TYPE LATCHES NXP
CD74HC373M96 OCTAL TRANSPARENT D-TYPE LATCHES NXP

Other Datasheets by Texas Instruments

Part Number Description
CD74HC10 Triple 3-Input NAND Gates
CD74HC107 Dual J-K Flip-Flop
CD74HC109 Dual J-K Flip-Flop
CD74HC10E Triple 3-Input NAND Gates
CD74HC11 Triple 3-Input AND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD74HC10, CD54HC10 SCHS128D – AUGUST 1997 – REVISED JULY 2021 CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 1A 1 1B 2 2A 3 2B 4 2C 5 2Y 6 GND 7 3 Description This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HC10M SOIC (14) 8.70 mm × 3.90 mm CD74HC10E PDIP (14) 19.30 mm × 6.40 mm CD54HC10F CDIP (14) 21.30 mm × 7.