CD74HCT640 Datasheet | Texas Instruments

Data sheet acquired from Harris Semiconductor SCHS192B January 1998 - Revised May 2003 CD54HC640, CD74HC640, CD54HCT640, CD74HCT640 High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting [ /Title (CD74 HC640 , CD74 HCT64 0) /Subject (High Speed CMOS Features Description - Buffered Inputs - Three-State Outputs - Applications in Multiple-Data-Bus Architecture - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH The ’HC640 and ’HCT640 silicon-gate CMOS three-state bidirectional inverting and non-inverting buffers are intended for two-way asynchronous munication between data buses. They have high drive current outputs which enable high-speed operation when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuits, and have speeds parable to low power Schottky TTL circuits. They can drive 15 LSTTL loads. The ’HC640 and ’HCT640 are inverting buffers. The direction of data flow (A to B, B to A) is controlled by the DIR input. Outputs are enabled by a low on the Output Enable input (OE); a high OE puts these devices in the high impedance...