CD74HCT646 Datasheet | Texas Instruments

CD54HC646, CD74HCT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCHS278B - APRIL 2003 - REVISED APRIL 2003 D 2-V to 6-V VCC Operation (CD54HC646) D 4.5-V to 5.5-V VCC Operation (CD74HCT646) D Wide Operating Temperature Range of - 55°C to 125°C D Balanced Propagation Delays and Transition Times D Standard Outputs Drive Up To 15 LS-TTL Loads D Significant Power Reduction pared to LS-TTL Logic ICs D Inputs Are TTL-Voltage patible (CD74HCT646) D Independent Registers for A and B Buses D Multiplexed Real-Time and Stored Data D True Data Paths CD54HC646 . . . F PACKAGE CD74HCT646 . . . M PACKAGE (TOP VIEW) CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 CLKBA 22 SBA 21 OE 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 B8 description/ordering information The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with these devices. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either or both registers. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be stored in one register and /or B data can be stored in the other register. When an output function is disabled, the input function still is enabled and can be used to store data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state during power up or power...