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CDC208 Datasheet Dual 1-line To 4-line Clock Drivers

Manufacturer: Texas Instruments

Overview: ąą D Low-Skew Propagation Delay Specifications for Clock-Driver Applications D TTL-Compatible Inputs and CMOS-Compatible Outputs D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND.

General Description

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2).

The device also offers two output-enable (OE1 and OE2) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

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