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CDC2509B - 3.3-V Phase-Lock-Loop Clock Driver

General Description

The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers.

They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

They are specifically designed for use with synchronous DRAMs.

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CDC2509B 3.