Datasheet Summary
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SCAS377E
- APRIL 1994
- REVISED JULY 2004
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
Features
- Low Output Skew for Clock-Distribution and Clock-Generation Applications
- Operates at 3.3-V VCC
- Distributes One Clock Input to Six Outputs
- One Select Input Configures Three Outputs to
Operate at One-Half or Double the Input Frequency
- No External RC Network Required
- On-Chip Series Damping Resistors
- External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
- Application for Synchronous DRAM, High-Speed Microprocessor
- TTL-patible Inputs and Outputs
- Outputs Drive 50-Ω Parallel-Terminated
Transmission Lines
- State-of-the-Ar...