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CDC2536 - 3.3-V Phase-Lock-Loop Clock Driver

General Description

The CDC2536 is a high-performance, low-skew, low-jitter clock driver.

It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal.

Key Features

  • Low Output Skew for Clock-Distribution and Clock-Generation.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CDC2536 www.ti.com SCAS377E – APRIL 1994 – REVISED JULY 2004 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS FEATURES • Low Output Skew for Clock-Distribution and Clock-Generation Applications • Operates at 3.