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CDC2510C - 3.3-V Phase-Lock-Loop Clock Driver

General Description

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

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Other Datasheets by Texas Instruments

Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
D Use CDCVF2510A as a Replacement for this Device D Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2 D Spread Spectrum Clock Compatible D Operating Frequency 25 MHz to 125 MHz D Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps D Drop-In Replacement for TI CDC2510A With Enhanced Performance D Jitter (cyc − cyc) at 66 MHz to 100 MHz is |100 ps| D Available in Plastic 24-Pin TSSOP D Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications D Distributes One Clock Input to One Bank of Ten Outputs D External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input D On-Chip Series Damping Resistors D No External RC Network Required D Operates at 3.3 V CDC2510C 3.