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CDCF5801 Datasheet Clock Multiplier

Manufacturer: Texas Instruments

Overview: Not Recommended for New Designs CDCF5801 www.ti.com SCAS698F – SEPTEMBER 2003 – REVISED APRIL 2006 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT (Not Recommended for New Designs Use CDCF5801A as a.

General Description

The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner.

For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge.

Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition.

Key Features

  • Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8.
  • Programmable Bidirectional Delay Steps of 1.3 mUI.
  • Output Frequency Range of 25 MHz to 280 MHz.
  • Input Frequency Range of 12.5 MHz to 240 MHz.
  • Low Jitter Generation.
  • Single-Ended REFCLK Input With Adjustable Trigger Level (Works With LVTTL, HSTL, and LVPECL).
  • Differential/Single-Ended Output.
  • Output Can Drive LVPECL, LVDS, and LVTTL.
  • Three Power Operating Modes to Minimiz.

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