CDCL1810A Description
The CDCL1810A is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: The CDCL1810A supports one differential LVDS clock input and a total of 10 differential CML outputs.
CDCL1810A Key Features
- 1 Single 1.8 V Supply
- High-Performance Clock Distributor with 10
- Low Input-to-Output Additive Jitter: as low as 10fs
- Low-Voltage Differential Signaling (LVDS) Input
- Differential Current Mode Logic (CML) Outputs, 50Ω Single-Ended On-Chip Termination, up to 650 MHz Frequency
- Two Groups of Five Outputs Each with Independent Frequency Division Ratios
- Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements
- Power Consumption: 410 mW Typical
- Output Enable Control for Each Output
- SDA/SCL Device Management Interface
CDCL1810A Applications
- Clock Distribution for High-Speed SERDES
- Distribution of SERDES Reference Clocks for
- Up to 1-to-10 Clock Buffering and Fan-out