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CDCLVD1213 - 1:4 Low Additive Jitter LVDS Buffer

General Description

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution.

The input can either be LVDS, LVPECL, or CML.

Key Features

  • 1 1:4 Differential Buffer.
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20- MHz.
  • Low Output Skew of 20 ps (Maximum).
  • Selectable Divider Ratio 1, /2, /4.
  • Universal Input Accepts LVDS, LVPECL, and CML.
  • 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible.
  • Clock Frequency: Up to 800 MHz.
  • Device Power Supply: 2.375 V to 2.625 V.
  • Industrial Temperature Range:.
  • 40°C to 85°C.
  • Packaged in 3 mm × 3 mm, 16.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVD1213 SCAS897A – JULY 2010 – REVISED OCTOBER 2016 CDCLVD1213 1:4 Low Additive Jitter LVDS Buffer With Divider 1 Features •1 1:4 Differential Buffer • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20- MHz • Low Output Skew of 20 ps (Maximum) • Selectable Divider Ratio 1, /2, /4 • Universal Input Accepts LVDS, LVPECL, and CML • 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible • Clock Frequency: Up to 800 MHz • Device Power Supply: 2.375 V to 2.