CDCLVD1216 Datasheet | Texas Instruments

CDCLVD1216 .ti. SCAS900B - OCTOBER 2010 - REVISED JANUARY 2011 2:16 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1216 Features 1 - 2:16 Differential Buffer - Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz - Low Output Skew of 55 ps (Max) - Universal Inputs Accept LVDS, LVPECL, LVCMOS - Selectable Clock Inputs Through Control Pin - 16 LVDS Outputs, ANSI EIA/TIA-644A Standard patible - Clock Frequency up to 800 MHz - 2.375- 2.625V Device Power Supply - LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs - Industrial Temperature Range - 40°C to 85°C - Packaged in 7mm × 7mm 48-Pin QFN (RGZ) - ESD Protection Exceeds 3 kV HBM, 1 kV CDM APPLICATIONS - Telemunications/Networking - Medical Imaging - Test and Measurement Equipment - Wireless munications...