CDCLVD1216
Overview
The CDCLVD1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVD1216 can accept two clock sources into an input multiplexer.
- 2:16 Differential Buffer
- Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz
- Low Output Skew of 55 ps (Max)
- Universal Inputs Accept LVDS, LVPECL, LVCMOS
- Selectable Clock Inputs Through Control Pin
- 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
- Clock Frequency up to 800 MHz
- 2.375-2.625V Device Power Supply
- LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
- Industrial Temperature Range -40°C to 85°C
