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CDCU877 - 1.8-V PHASE LOCK LOOP CLOCK DRIVER

General Description

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT).

Key Features

  • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CDCU877, CDCU877A www.ti.com FEATURES • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications • Spread Spectrum Clock Compatible • Operating Frequency: 10 MHz to 400 MHz • Low Current Consumption: <135 mA • Low Jitter (Cycle-Cycle): ±30 ps • Low Output Skew: 35 ps • Low Period Jitter: ±20 ps • Low Dynamic Phase Offset: ±15 ps 1.