CDCU877 Datasheet | Texas Instruments

FEATURES - 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications - Spread Spectrum Clock patible - Operating Frequency: 10 MHz to 400 MHz - Low Current Consumption: <135 m A - Low Jitter (Cycle-Cycle): ±30 ps - Low Output Skew: 35 ps - Low Period Jitter: ±20 ps - Low Dynamic Phase Offset: ±15 ps 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D - JUNE 2005 - REVISED JULY 2007 - Low Static Phase Offset: ±50 ps - Distributes One Differential Clock Input to Ten Differential Outputs - 52-Ball μBGA (Micro Star™ Junior BGA, 0,65-mm pitch) and 40-Pin MLF - External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks - Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300 - Fail-Safe Inputs DESCRIPTION The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on,...