Datasheet4U Logo Datasheet4U.com

CDCUA877 - 1.8-V PHASE LOCK LOOP CLOCK DRIVER

General Description

The CDCUA877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT).

Key Features

  • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II).

📥 Download Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CDCUA877 www.ti.com SCAS769A – AUGUST 2006 – REVISED JUNE 2007 1.8-V PHASE LOCK LOOP CLOCK DRIVER FEATURES • 1.8-V/1.