DAC5687-EP
FEATURES
- Controlled Baseline
- One Assembly
- One Test Site
- One Fabrication Site
- Extended Temperature Performance of
- 55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree (1)
- 500 MSPS
- Selectable 2×- 8× Interpolation
- On-Chip PLL/VCO Clock Multiplier
- Full IQ pensation Including Offset, Gain, and Phase
- Flexible Input Options
- FIFO With Latch on External or Internal Clock
- Even/Odd Multiplexed Input
- Single-Port Demultiplexed Input
- plex Mixer With 32-Bit Numerically Controlled Oscillator (NCO)
- Fixed-Frequency Mixer With Fs/4 and Fs/2
- 1.8-V or 3.3-V I/O Voltage
- On-Chip 1.2-V Reference
- Differential Scalable Output: 2 m A to 20 m A
- Pin patible to DAC5686
- High Performance
- 81-d Bc Adjacent Channel Leakage Ratio (ACLR) WCDMA TM1 at 30.72 MHz
- 72-d Bc ACLR WCDMA TM1 at 153.6 MHz
- Package: 100-Pin HTQFP
(1) ponent qualification in accordance with JEDEC and industry standards to...
