Datasheet Details
| Part number | DS90CR286AT-Q1 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 2.08 MB |
| Description | 3.3 V Rising Edge Data Strobe LVDS Receiver |
| Datasheet |
 DS90CR286AT-Q1 Datasheet
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General Description
The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data.
The receiver data outputs strobe on the output clock's rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz.
Key Features
- 1 20 to 66 MHz Shift Clock Support.
- 50% Duty Cycle on Receiver Output Clock.
- Best.
- in.
- Class Setup & Hold Times on Rx Outputs.
- Rx Power Consumption < 270 mW (typ) at 66 MHz Worst Case.
- Rx Power-down Mode < 200 μW (max).
- ESD Rating: 4 kV (HBM), 1 kV (CDM).
- PLL Requires No External Components.
- Compatible with TIA/EIA-644 LVDS Standard.
- Low Profile 56-Pin DGG (TSSOP) Package.
- Operating Temperatur.