DS90CR561 Overview
The DS90CR561 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted.
DS90CR561 Key Features
- 2 Up to 105 Megabyte/sec bandwidth
- Narrow bus reduces cable size and cost
- 290 mV swing LVDS devices for low EMI
- Low power CMOS design
- Power-down mode
- PLL requires no external ponents
- Low profile 48-lead TSSOP package
- Rising edge data strobe
- patible with TIA/EIA-644 LVDS standard
