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LMK00306 - 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

General Description

The LMK00306 is a 3-GHz, 6-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation.

The input clock can be selected from two universal inputs or one crystal input.

Key Features

  • 1 3:1 Input Multiplexer.
  • Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks.
  • One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock.
  • Two Banks with 3 Differential Outputs Each.
  • LVPECL, LVDS, HCSL, or Hi-Z (Selectable Per Bank).
  • LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz:.
  • 20 fs RMS (10 kHz to 1 MHz).
  • 51 fs RMS (12 kHz to 20 MH.

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Datasheet Details

Part number LMK00306
Manufacturer Texas Instruments
File Size 1.91 MB
Description 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator
Datasheet download datasheet LMK00306 Datasheet

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Other Datasheets by Texas Instruments

Part Number Description
LMK00301 3-GHz 10-Output Ultra-Low Additive Jitter Differential Clock Buffer and Level Translator
LMK00304 3-GHz 4-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator
LMK00308 3-GHz 8-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator
LMK00334 Four-Output Clock Buffer and Level Translator
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LMK00306 SNAS578D – FEBRUARY 2012 – REVISED MARCH 2016 LMK00306 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator 1 Features •1 3:1 Input Multiplexer – Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks – One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock • Two Banks with 3 Differential Outputs Each – LVPECL, LVDS, HCSL, or Hi-Z (Selectable Per Bank) – LVPECL Additive Jitter with LMK03806 Clock Source at 156.25 MHz: – 20 fs RMS (10 kHz to 1 MHz) – 51 fs RMS (12 kHz to 20 MHz) • High PSRR: -65 / -76 dBc (LVPECL/LVDS) at 156.