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LMK00804B - Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer

General Description

The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5V levels) from one of two selectable inputs, which can accept differential or single-ended inputs.

Key Features

  • 1 Four LVCMOS/LVTTL Outputs with 7 Ω Output Impedance.
  • Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz.
  • Noise Floor:.
  • 166 dBc/Hz (typ) @ 125 MHz.
  • Output Frequency: 350 MHz (max).
  • Output Skew: 35 ps (max).
  • Part-to-Part Skew: 700 ps (max).
  • Two Selectable Inputs.
  • CLK, nCLK Pair Accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL.
  • LVCMOS_CLK Accepts LVCMOS/LVTTL.
  • Synchronous Clock Enable.
  • Co.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer 1 Features •1 Four LVCMOS/LVTTL Outputs with 7 Ω Output Impedance – Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz – Noise Floor: –166 dBc/Hz (typ) @ 125 MHz – Output Frequency: 350 MHz (max) – Output Skew: 35 ps (max) – Part-to-Part Skew: 700 ps (max) • Two Selectable Inputs – CLK, nCLK Pair Accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL – LVCMOS_CLK Accepts LVCMOS/LVTTL • Synchronous Clock Enable • Core/Output Power Supplies: – 3.3 V/3.3 V – 3.3 V/2.5 V – 3.3 V/1.8 V – 3.3 V/1.