LMK00804B Overview
The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs...
LMK00804B Key Features
- 1 Four LVCMOS/LVTTL Outputs with 7 Ω Output Impedance
- Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz
- Noise Floor: -166 dBc/Hz (typ) @ 125 MHz
- Output Frequency: 350 MHz (max)
- Output Skew: 35 ps (max)
- Part-to-Part Skew: 700 ps (max)
- Two Selectable Inputs
- CLK, nCLK Pair Accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL
- LVCMOS_CLK Accepts LVCMOS/LVTTL
- Synchronous Clock Enable