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LMK03318 Datasheet Ultra-low-noise Jitter Clock Generator

Manufacturer: Texas Instruments

Overview: Product Folder Order Now Technical Documents Tools & Software Support & Community LMK03318 SNAS669E – SEPTEMBER 2015 – REVISED APRIL 2018 LMK03318 Ultra-Low-Noise Jitter Clock Generator Family With One PLL, Eight.

General Description

The LMK03318 device is an ultra-low-noise PLLATINUM™ clock generator with one fractional-N frequency synthesizer with integrated VCO, flexible clock distribution and fanout, and pin-selectable configuration states stored in on-chip EEPROM.

The device can generate multiple clocks for various multigigabit serial interfaces and digital devices, thus reducing BOM cost and board area and improving reliability by replacing multiple oscillators and clock distribution devices.

The ultra-low jitter reduces biterror rate (BER) in high-speed serial links.

Key Features

  • 1 Ultra-Low Noise, High Performance.
  • Jitter: 100-fs RMS Typical, FOUT > 100 MHz.
  • PSNR:.
  • 80 dBc, Robust Supply Noise Immunity.
  • Flexible Device Options.
  • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination.
  • Pin Mode, I2C Mode, EEPROM Mode.
  • 71-Pin Selectable Pre-programmed Default Start-Up Options.
  • Dual Inputs With Automatic or Manual Selection.
  • Crystal Input: 10 to 52 MHz.
  • Ex.

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