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SM320C6712C-EP - Digital Signal Processor

This page provides the datasheet information for the SM320C6712C-EP, a member of the SM320C6712-EP Digital Signal Processor family.

Datasheet Summary

Description

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Features

  • Hardware Support for IEEE Single-Precision and Double-Precision Instructions.
  • Byte-Addressable (8-, 16-, 32-Bit Data).
  • 8-Bit Overflow Protection.
  • Saturation.
  • Bit-Field Extract, Set, Clear.
  • Bit-Counting.
  • Normalization D Device Configuration.
  • Boot Mode: 8- and 16-Bit ROM Boot.
  • Endianness: Little Endian (12/12C) Little Endian, Big Endian (12D) SGUS055.

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Datasheet preview – SM320C6712C-EP

Datasheet Details

Part number SM320C6712C-EP
Manufacturer Texas Instruments
File Size 1.44 MB
Description Digital Signal Processor
Datasheet download datasheet SM320C6712C-EP Datasheet
Additional preview pages of the SM320C6712C-EP datasheet.

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Full PDF Text Transcription

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SM320C6712ĆEP, SM320C6712CĆEP, SM320C6712DĆEP FLOATINGĆPOINT DIGITAL SIGNAL PROCESSORS D Controlled Baseline − One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Low-Price/High-Performance Floating-Point Digital Signal Processors (DSPs): 320C67x (SM320C6712, C6712C, C6712D) − Eight 32-Bit Instructions/Cycle − 100-, 167-MHz Clock Rates − 10-, 6-ns Instruction Cycle Times − 600, 1000 MFLOPS D Advanced Very Long Instruction Word (VLIW) C67x DSP Core − Eight Highly Independent Functional Units: − Four ALUs (Floating- and Fixed-Point) − Two ALUs (Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − I
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