SN10KHT5573 Overview
This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The eight latches of the SN10KHT5573 are transparent D-type latches. While latch enable (LE) is low, the Q outputs follow the data (D) inputs.