SN65DSI86-Q1 Description
The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge.
SN65DSI86-Q1 Key Features
- Implements MIPI® D-PHY Version 1.1 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
- Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1.5 Gbp
- Supports 18 bpp and 24 bpp DSI Video Packets With RGB666 and RGB888 Formats
- MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configuration
- Supports Dual-Channel DSI Odd, Even and Left, Right Operating Modes
- 1.2-V Main VCC Power Supply and 1.8-V Supply for Digital I/Os
- Low-Power Features Include Panel Refresh and MIPI Ultralow Power State (ULPS) Support
- DisplayPort Lane Polarity and Assignment Configurable
- Supports 12-MHz, 19.2-MHz, 26-MHz, 27-MHz, and 38.4-MHz Frequencies Through External Reference Clock (REFCLK)
- ESD Rating ±2 kV (HBM)