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SN65LVDS302 Datasheet Programmable 27-bit Serial-to-parallel Receiver

Manufacturer: Texas Instruments

Overview: .ti. SN65LVDS302 SLLS733E – JUNE 2006 – REVISESDNO6C5TLOVBDERS2300220 SLLS733E – JUNE 2006 – REVISED OCTOBER 2020 SN65LVDS302 Programmable 27-Bit Serial-to-Parallel Receiver.

General Description

The SN65LVDS302 receiver de-serializes FlatLink™3G pliant serial input data to 27 parallel data outputs.

The SN65LVDS302 receiver contains one shift register to load 30 bits from 1, 2 or 3 serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit.

If the parity check confirms correct parity, the Channel Parity Error (CPE) output remains low.

Key Features

  • Serial interface technology.
  • Compatible with FlatLink™3G such as SN65LVDS301.
  • Supports video interfaces up to 24-bit RGB data and 3 control bits received over 1, 2 or 3 SubLVDS differential lines.
  • SubLVDS differential voltage levels.
  • Up to 1.755-Gbps Data Throughput.
  • Three operating modes to conserve power.
  • Active mode QVGA: 17 mW.
  • Typical shutdown: 0.7 μW.
  • Typical standby mode: 27 μW Typical.
  • Bus-swap fun.

More Datasheets from Texas Instruments

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SN65LVDS314 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER

SN65LVDS302 Distributor