SN65LVDS308 Overview
The SN65LVDS308 receiver deserializes FlatLink 3G-pliant serial input data to 27 parallel data outputs. The SN65LVDS308 receiver contains one shift register to load 30 bits from two serial inputs and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel.
SN65LVDS308 Key Features
- FlatLink 3G Serial Interface Technology
- patible With FlatLink™ 3G Transmitters
- Supports Video Interfaces up to 24-Bit RGB Data and 3 Control Bits Received Over Two Differential Data Lines
- SubLVDS Differential Voltage Levels
- Up to 810-Mbps Data Throughput
- Three Operating Modes to Conserve Power
- Active mode VGA 60 fps: 17 mW
- Typical Shutdown: 0.7 µW
- Typical Standby Mode: 67 µW Typical
- ESD Rating > 4 kV (HBM)