SN65LVDS84AQ-Q1 Datasheet | Texas Instruments

FEATURES - 2 21:3 Data Channel pression at up to 196 Mbytes/s Throughput - Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI - 21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs - Operates From a Single 3.3-V Supply and 89 m W (Typ) - Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch - Consumes Less Than 0.54 m W When Disabled - Wide Phase-Lock Input Frequency Range: 31 MHz to 75 MHz - No External ponents Required for PLL - Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard - SSC Tracking Capability of 3% Center Spread at 50-k Hz Modulation Frequency - Improved Replacement for SN75LVDS84 and NSC DS90CF363A 3-V Device - Qualified for Automotive Applications DGG PACKAGE (TOP VIEW) D4 1 VCC 2 D5 3 D6 4 GND 5 D7 6 D8 7 VCC 8 D9 9 D10 10 GND 11 D11 12 D12 13 NC 14 D13 15 D14 16 GND 17 D15 18 D16 19 D17 20 VCC 21 D18 22 D19 23 GND 24 48 D3 47 D2 46 GND 45 D1 44 D0 43 NC 42 LVDSGND 41 Y0M 40 Y0P 39 Y1M 38 Y1P 37 LVDSVCC 36 LVDSGND 35 Y2M 34 Y2P 33 CLKOUTM 32 CLKOUTP 31 LVDSGND 30 PLLGND 29 PLLVCC 28 PLLGND 27 SHTDN 26 CLKIN 25 D20 - Not Connected DESCRIPTION /ORDERING INFORMATION The SN65LVDS84AQ Flat Link™ transmitter contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a patible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits D0- D20 are each loaded into registers of the SN65LVDS84AQ upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency...