SN74AS194 Datasheet | Texas Instruments

description These 4-bit bidirectional universal shift registers feature parallel outputs, right-shift and left-shift serial (SR SER, SL SER) inputs, operatingmode-control (S0, S1) inputs, and a direct overriding clear (CLR) line. The registers have four distinct modes of operation: - Inhibit clock (temporary data latch/do nothing) - Shift right (in the direction QA toward QD) - Shift left (in the direction QD toward QA) - Parallel (broadside) load SN54AS194 . . . FK PACKAGE (TOP VIEW) SR SER CLR NC VCC QA 3 2 1 20 19 B5 17 QC NC 6 16 NC C7 15 QD D8 14 CLK 9 10 11 12 13 SL SER GND NC S0 S1 Parallel synchronous loading is acplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited. - No internal connection Shift right is acplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low. The SN54AS194 is characterized for operation over the full military temperature range of - 55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1994, Texas Instruments Incorporated - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 - POST OFFICE BOX 1443 HOUSTON, TEXAS 77251- 1443 SN54AS194, SN74AS194 ą 4ĆBIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS ą SDAS212A - DECEMBER 1983 - REVISED DECEMBER...