SN74CBTLV3857 Datasheet | Texas Instruments

description /ordering information This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE) input levels. When OE is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-kΩ pulldown resistors to ground on the B port. The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. ORDERING INFORMATION PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING QSOP - DBQ Tape and reel SN74CBTLV3857DBQR CL857 SOIC - DW - 40°C to 85°C Tube Tape and reel SN74CBTLV3857DW SN74CBTLV3857DWR CBTLV3857 TSSOP - PW Tape and reel SN74CBTLV3857PWR CL857 TVSOP - DGV Tape and reel SN74CBTLV3857DGVR CL857 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at .ti./sc/package. FUNCTION TABLE INPUT OE FUNCTION A port = B port Disconnect Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  2003, Texas Instruments Incorporated 1 SN74CBTLV3857 LOWĆVOLTAGE 10ĆBIT FET BUS SWITCH WITH INTERNAL PULLDOWN RESISTORS SCDS085E - OCTOBER 1998 - REVISED OCTOBER 2003 logic diagram (positive...