SN74LV595A-EP Datasheet | Texas Instruments

D Controlled Baseline - One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D 2-V to 5.5-V VCC Operation D Max tpd of 7.4 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C † ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. SN74LV595AĆEP 8ĆBIT SHIFT REGISTER WITH 3ĆSTATE OUTPUT REGISTERS SCLS568B - JANUARY 2004 - REVISED MAY 2004 D Supports Mixed-Mode Voltage Operation on All Ports D 8-Bit Serial-In, Parallel-Out Shift D Ioff Supports Partial-Power-Down Mode Operation D Shift Register Has Direct Clear PW PACKAGE (TOP VIEW) QB QC QD QE QF QG QH GND 1 2 3 4 5 6 7 8 16 VCC 15 QA 14 SER 13 OE 12 RCLK 11 SRCLK 10 SRCLR 9 QH′ description/ordering information The SN74LV595A is an 8-bit shift register designed for 2-V to 5.5-V VCC operation. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs except QH′ are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together,...