SN74LV595A Description
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. SN74LV595A SCLS414T APRIL 1998 REVISED MARCH 2023 .ti.
SN74LV595A Key Features
- VCC operation of 2 V to 5.5 V
- Maximum tpd of 7.1 ns at 5 V
- Typical VOLP (output ground bounce)
- Typical VOHV (output VOH undershoot)
- Support mixed-mode voltage operation on all ports
- 8-bit serial-in, parallel-out shift
- Ioff supports live insertion, partial power-down
- Shift register has direct clear
- Latch-up performance exceeds 250 mA per JESD