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SN74LVC16373A-EP - 16-Bit Transparent D-Type Latch

Description

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

Features

  • Member of the Texas Instruments Widebus™ Family.
  • Operates From 1.65 V to 3.6 V.
  • Inputs Accept Voltages to 5.5 V.
  • Max tpd of 4.2 ns at 3.3 V.
  • Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C.
  • Ioff Supports Partial-Power-Down Mode Operation.
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC).
  • Latc.

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Datasheet preview – SN74LVC16373A-EP

Datasheet Details

Part number SN74LVC16373A-EP
Manufacturer Texas Instruments
File Size 516.08 KB
Description 16-Bit Transparent D-Type Latch
Datasheet download datasheet SN74LVC16373A-EP Datasheet
Additional preview pages of the SN74LVC16373A-EP datasheet.

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Full PDF Text Transcription

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www.ti.com SN74LVC16373A-EP 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS825 – JUNE 2006 FEATURES • Member of the Texas Instruments Widebus™ Family • Operates From 1.65 V to 3.6 V • Inputs Accept Voltages to 5.5 V • Max tpd of 4.2 ns at 3.3 V • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ ORDERING INFORMATION This 16-bit transparent D-type latch is designed for 1.65-V to 3.
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