SN74LVC2G08-EP Datasheet | Texas Instruments

.ti. SN74LVC2G08-EP DUAL 2-INPUT POSITIVE-AND GATE SGDS032 - SEPTEMBER 2007 Features - Controlled Baseline - One Assembly - One Test Site - One Fabrication Site - Enhanced Diminishing Manufacturing Sources (DMS) Support - Enhanced Product-Change Notification - Qualification Pedigree (1) - Supports 5-V VCC Operation - Inputs Accept Voltages to 5.5 V - Max tpd of 5.7 ns at 3.3 V - Low Power Consumption, 10 μA Max ICC - ±24 m A Output Drive at 3.3 V - Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C (1) ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. - Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 1000-V Charged-Device Model (C101) DCU PACKAGE (TOP VIEW) 1A 1B 2Y GND 1 2 3 4 8 VCC 7 1Y 6 2B 5 2A See mechanical drawings for...