SN74LVC2G08-Q1 Datasheet | Texas Instruments

.ti. SCES557D - MARCH 2004 - REVISED MARCH 2010 DUAL 2-INPUT POSITIVE-AND GATE Check for Samples: SN74LVC2G08-Q1 Features - Qualified for Automotive Applications - Supports 5-V VCC Operation - Inputs Accept Voltages to 5.5 V - Max tpd of 4.7 ns at 3.3 V - Low Power Consumption, 10-μA Max ICC - ±24-m A Output Drive at 3.3 V - Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 1000-V Charged-Device Model (C101) DCT Package (Top View) 1A 1B 2Y GND 1 2 3 4 8 VCC 7 1Y 6 2B 5 2A P0147-01 DESCRIPTION/ORDERING INFORMATION This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G08-Q1 performs the Boolean function Y + A - B or Y + A ) B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered...