SN75LVDS32 Datasheet | Texas Instruments

SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS D Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard D Operates With a Single 3.3-V Supply D Designed for Signaling Rate of up to 155 Mbps D Differential Input Thresholds ± 100 m V Max D Low-Voltage TTL (LVTTL) Logic Output Levels D Open-Circuit Fail Safe D Characterized For Operation From 0°C to 70°C SLLS360B - JUNE 1999 - REVISED JUNE 2001 SN75LVDS32D (Marked as 75LVDS32) SN75LVDS32PW (Marked as DS32) (TOP VIEW) 1B 1 1A 2 1Y 3 G4 2Y 5 2A 6 2B 7 GND 8 16 VCC 15 4B 14 4A 13 4Y 12 G 11 3Y 10 3A 9 3B description The SN75LVDS32 and SN75LVDS9637 are SN75LVDS9637D (Marked as DF637 or 7L9637) SN75LVDS9637DGK (Marked as AXI) (TOP VIEW) differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce VCC 1 1Y 2 2Y 3 GND 4 8 1A 7 1B 6 2A 5 2B the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 m V allow operation with a differential input voltage within the input mon-mode voltage range. The input mon-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability,...