TDA4AP-Q1 Datasheet | Texas Instruments

TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 SPRSP79B - FEBRUARY 2023 - REVISED DECEMBER 2023 TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 Jacinto™ Processors 1 Features Processor cores: - Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS - Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz - Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators - Depth and Motion Processing Accelerators (DMPAC) - Eight Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz - 2MB shared L2 cache per quad-core Cortex®A72 cluster - 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 core - Eight Arm® Cortex®-R5F MCUs at up to 1.0 GHz - 16K I-Cache, 16K D-Cache, 64K L2 TCM - Two Arm® Cortex®-R5F MCUs in isolated MCU subsystem - Six Arm® Cortex®-R5F MCUs in general pute partition - GPU IMG BXS-4-64, 256k B Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s - Custom-designed interconnect fabric supporting near max processing entitlement Memory subsystem: - Up to 8MB of on-chip L3 RAM with ECC and coherency - ECC error protection - Shared coherent cache - Supports internal DMA engine - Up to Four External Memory Interface (EMIF) module with ECC - Supports LPDDR4 memory types - Supports speeds up to 4266 MT/s - Up to 4x32-b bus with inline ECC up to 68...