TDA4AP-Q1 Overview
TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 SPRSP79B FEBRUARY 2023 REVISED DECEMBER 2023 TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 Jacinto™ Processors.
TDA4AP-Q1 Key Features
- Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
- Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
- Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Eight Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz
- 2MB shared L2 cache per quad-core Cortex®A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 core
- Eight Arm® Cortex®-R5F MCUs at up to 1.0 GHz
- 16K I-Cache, 16K D-Cache, 64K L2 TCM
- Two Arm® Cortex®-R5F MCUs in isolated MCU
TDA4AP-Q1 Applications
- Documentation available to aid ISO 26262
- Systematic capability up to ASIL-D/SIL-3 targeted
- Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
- Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
- Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain