Datasheet4U Logo Datasheet4U.com

TDA4VH-Q1 - Jacinto Processors

Features

  • Processor cores:.
  • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS.
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz.
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators.
  • Depth and Motion Processing Accelerators (DMPAC).
  • Eight Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz.
  • 2MB shared L2 cache p.

📥 Download Datasheet

Datasheet preview – TDA4VH-Q1

Datasheet Details

Part number TDA4VH-Q1
Manufacturer Texas Instruments
File Size 5.73 MB
Description Jacinto Processors
Datasheet download datasheet TDA4VH-Q1 Datasheet
Additional preview pages of the TDA4VH-Q1 datasheet.

📁 Similar Datasheet

  • TDA4001 - AM Receiver IC with Demodulator (Infineon)
  • TDA4010 - AM RECEIVER (Infineon Technologies)
  • TDA4050B - Infrarot-Vorverstarker (Siemens Semiconductor)
  • TDA4092 - 5 BIT BINARY TO 7-SEGMENT DECODER DRIVER (ST Microelectronics)
  • TDA4173 - TV Vertical Deflection Output Amplifier (Vishay Telefunken)
  • TDA4190 - TV SOUND CHANNEL WITH DC CONTROLS (ST Microelectronics)
  • TDA4200-3 - FM IF (Infineon Technologies AG)
  • TDA4210 - FM IF Limiter Amplifier and Detector (Telefunken Microelectronics)
  • TDA4210-3 - FM IF IC WITH SEARCH TUNING STOP PULSE/ FIELD STRENGTH INDICATOR/ MUTE SETTING AND MULTIPATH (Siemens Semiconductor)
  • TDA4250B - PROGRAMMABLE OPERATIONAL AMPLIFIER (Philips)
Other Datasheets by Texas Instruments

Full PDF Text Transcription

Click to expand full text
TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 SPRSP79B – FEBRUARY 2023 – REVISED DECEMBER 2023 TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 Jacinto™ Processors 1 Features Processor cores: • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators • Depth and Motion Processing Accelerators (DMPAC) • Eight Arm® Cortex®-A72 microprocessor subsystem at up to 2.0 GHz – 2MB shared L2 cache per quad-core Cortex®A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 core • Eight Arm® Cortex®-R5F MCUs at up to 1.
Published: |