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TPIC1321L - 3-Half H-Bridge Gate-Protected Logic-Level Power DMOS Array

General Description

GND 6 GATE5 7 19 DRAIN2 18 OUTPUT2 The TPIC1321L is a monolithic gate-protected SOURCE6 8 17 OUTPUT2 logic-level power DMOS array that consists of six SOURCE6 9 16 GATE2 electrically isolated N-channel enhancement- GATE6 10 15 DRAIN3 mode DMOS transistors configured as 3-half OUTPUT3 11

Key Features

  • integrated OUTPUT3 12 13 GATE3 high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor. The TPIC1321L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature of.
  • 40°C to 125°C. schematic 21, 22 DRAIN1 Q1.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ą TPIC1321L 3ĆHALF HĆBRIDGE GATEĆPROTECTED LOGICĆLEVEL POWER DMOS ARRAY SLIS042 − NOVEMBER 1994 • Low rDS(on) . . . 0.35 Ω Typ • Voltage Output . . . 60 V DW PACKAGE (TOP VIEW) • Input Protection Circuitry . . . 18 V OUTPUT1 1 24 OUTPUT1 • Pulsed Current . . . 4 A Per Channel • Extended ESD Capability . . . 4000 V • Direct Logic-Level Interface GATE4 2 SOURCE4 3 SOURCE4 4 GND 5 23 GATE1 22 DRAIN1 21 DRAIN1 20 DRAIN2 description GND 6 GATE5 7 19 DRAIN2 18 OUTPUT2 The TPIC1321L is a monolithic gate-protected SOURCE6 8 17 OUTPUT2 logic-level power DMOS array that consists of six SOURCE6 9 16 GATE2 electrically isolated N-channel enhancement- GATE6 10 15 DRAIN3 mode DMOS transistors configured as 3-half OUTPUT3 11 14 DRAIN3 H-bridges.