Description
GND 6 GATE5 7
19 DRAIN2 18 OUTPUT2
The TPIC1321L is a monolithic gate-protected
SOURCE6 8
17 OUTPUT2
logic-level power DMOS array that consists of six
SOURCE6 9
16 GATE2
electrically isolated N-channel enhancement-
GATE6 10 15 DRAIN3
mode DMOS transistors configured as 3-half
OUTPUT3 11
Features
- integrated
OUTPUT3 12 13 GATE3
high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to
4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ
resistor. The TPIC1321L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature of.
- 40°C to 125°C. schematic
21, 22 DRAIN1
Q1.
TPIC1321L Datasheet
