TPIC5424L Datasheet | Texas Instruments

description The TPIC5424L is a monolithic logic-level power DMOS array that consists of four electrically isolated N-channel enhancement-mode DMOS transistors, two of which are configured with a mon source. DW PACKAGE (TOP VIEW) GND SOURCE4/GND GATE4 NC DRAIN4 SOURCE3 DRAIN3 GATE3 NC NC 1 2 3 4 5 6 7 8 9 10 20 SOURCE2/GND 19 GATE2 18 NC 17 NC 16 DRAIN2 15 SOURCE1 14 DRAIN1 13 GATE1 12 NC 11 NC The TPIC5424L is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body surface-mount (DW) package. The TPIC5424L is characterized for operation over the case temperature range of - 40°C to 125°C. - No internal connection NE PACKAGE (TOP VIEW) DRAIN2 SOURCE2/GND GATE2 GND GND GATE4 SOURCE4/GND DRAIN4 1 2 3 4 5 6 7 8 16 SOURCE1 15 DRAIN1 14 GATE1 13 GND 12 GND 11 GATE3 10 DRAIN3 9 SOURCE3 schematic DRAIN1 GATE1 Q1 Z1 D1 D2 DRAIN3 Q3 Z3 GATE3 SOURCE1 DRAIN2 GATE2 Q2 Z2 SOURCE3 DRAIN4 Q4 Z4 GATE4 GND, SOURCE2, SOURCE4 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1994, Texas Instruments Incorporated - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 - POST OFFICE BOX 1443 HOUSTON, TEXAS 77251- 1443 TPIC5424L HĆBRIDGE LOGICĆLEVEL POWER DMOS ARRAY...