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74AHC257 - Quad 2-input multiplexer

General Description

The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Key Features

  • I Balanced propagation delays I All inputs have Schmitt-trigger actions I Non-inverting data path I Inputs accept voltages higher than VCC I Input levels: N For 74AHC257: CMOS level N For 74AHCT257: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from.
  • 40 °C to +85 °C and from.
  • 40 °C to +125 °C Nexperia 74AHC257; 74AHCT257 Quad 2-input multiplexer;.

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Datasheet Details

Part number 74AHC257
Manufacturer Nexperia
File Size 584.33 KB
Description Quad 2-input multiplexer
Datasheet download datasheet 74AHC257 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AHC257; 74AHCT257 Quad 2-input multiplexer; 3-state Rev. 02 — 9 May 2008 Product data sheet 1. General description The 74AHC257; 74AHCT257 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC257; 74AHCT257 has four identical 2-input multiplexers with 3-state outputs, which select 4 bits of data from two sources and are controlled by a common data select input (S). The data inputs from source 0 (1I0 to 4I0) are selected when input S is LOW and the data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected inputs.