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74AHCT02D Datasheet PDF

Nexperia 74AHCT02D

The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
Part No. 74AHCT02D
Datasheet 74AHCT02D Download
Manufacturer
Nexperia
Description Quad 2-input NOR gate
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74AHCT02D datasheet page 1 preview

FEATURES AND BENEFITS

● Balanced propagation delays
● All inputs have a Schmitt-trigger action
● Inputs accept voltages higher than VCC
● Input levels:
● For 74AHC02: CMOS level
● For 74AHCT02: TTL level
● ESD protection:
● HBM EIA/JESD22-A114E exceeds 2000 V
● MM EIA/JESD22-A115-A exceeds 200 V
● CDM EIA/JESD22-C101C exceeds 1000 V
● Multiple package options
● Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC02D -40 °C to +125 °C SO14 74AHCT02D 74AHC02PW -40 °C to +125 °C TSSOP14 74AHCT02PW 74AHC02BQ -40 °C to +125 °C DHVQFN14 74AHCT02BQ

DESCRIPTION

plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 4. Functional diagram 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 1Y 1 2Y 4 3Y 10 4Y 13 mna216 Fig.
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