74AHCT02PW Overview
74AHCT02 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 74AHCT02 provides a quad 2-input NOR function.
74AHCT02PW Key Features
- Balanced propagation delays
- All inputs have a Schmitt-trigger action
- Inputs accept voltages higher than VCC
- Input levels
- For 74AHC02: CMOS level
- For 74AHCT02: TTL level
- ESD protection
- HBM EIA/JESD22-A114E exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V
- CDM EIA/JESD22-C101C exceeds 1000 V
