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74AHCT377-Q100 - Octal D-type flip-flop

Download the 74AHCT377-Q100 datasheet PDF. This datasheet also covers the 74AHC377-Q100 variant, as both devices belong to the same octal d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC377-Q100; 74AHCT377-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Key Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1).
  • Specified from 40 C to +85 C and from 40 C to +125 C.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger actions.
  • Inputs accept voltages higher than VCC.
  • Ideal for addressable register.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC377-Q100-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Nexperia

Part Number Description
74AHCT377 Octal D-type flip-flop
74AHCT377D Octal D-type flip-flop
74AHCT377PW Octal D-type flip-flop
74AHCT374 Octal D-type flip-flop
74AHCT374-Q100 Octal D-type flip-flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AHC377-Q100; 74AHCT377-Q100 Octal D-type flip-flop with data enable; positive-edge trigger Rev. 1 — 3 December 2013 Product data sheet 1. General description The 74AHC377-Q100; 74AHCT377-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC377-Q100; 74AHCT377-Q100 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.