74AHCT374-Q100 Datasheet | Nexperia

74AHC374-Q100; Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 1 - 11 March 2014 Product data sheet 1. General description The 74AHC374-Q100; 74AHCT374-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A. The 74AHC374-Q100; 74AHCT374-Q100 prises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are mon to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold...