74AHCT374 Datasheet PDF (Octal D-type flip-flop)

74AHCT374 - Octal D-type flip-flop

This page provides the datasheet information for the 74AHCT374, a member of the 74AHC374 Octal D-type flip-flop family.

Description

The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is speciﬁed in compliance with JEDEC standard No.

7-A.

Features

I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Common 3-state output enable input I Input levels: N For 74AHC374: CMOS level N For 74AHCT374: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Speciﬁed from.
40 °C to +85 °C and from.
40 °C to +125 °C Nexperia 74AHC374; 74AHCT374 Octal D-type ﬂi.

Datasheet Details

Part number	74AHCT374
Manufacturer	nexperia
File Size	602.86 KB
Description	Octal D-type flip-flop
Datasheet	74AHCT374 Datasheet
Additional preview pages of the 74AHCT374 datasheet.

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Full PDF Text Transcription

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74AHC374; 74AHCT374 Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state Rev. 03 — 12 June 2008 Product data sheet 1. General description The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard No. 7-A. The 74AHC374; 74AHCT374 comprises eight D-type ﬂip-ﬂops featuring separate D-type inputs for each ﬂip-ﬂop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all ﬂip-ﬂops. The eight ﬂip-ﬂops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition. When OE is LOW the content of the eight ﬂip-ﬂops is available at the outputs.

Published: Apr 25, 2018 |