74AHCT74-Q100 Datasheet | Nexperia

description The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-Power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A. The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has plementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits - Automotive product qualification in accordance with AEC-Q100 (Grade 1) - Specified from -40 °C to +85 °C and from -40 °C to +125 °C - Balanced propagation delays - All inputs have Schmitt-trigger actions - Inputs accept voltages higher than VCC - Input levels: - For 74AHC74-Q100: CMOS level - For 74AHCT74-Q100: TTL level - ESD protection: - MIL-STD-883, method 3015 exceeds 2000 V - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V (C = 200 p F, R = 0 Ω) - Multiple package options - DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints Nexperia 74AHC74-Q100; 74AHCT74-Q100 Dual D-type flip-flop with set and reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC74D-Q100 -40 °C to +125 °C SO14 74AHCT74D-Q100 74AHC74PW-Q100 -40 °C to +125 °C TSSOP14 74AHCT74PW-Q100 74AHC74BQ-Q100 -40 °C to +125 °C DHVQFN14 74AHCT74B...